This invention relates to packaging of integrated circuits in packages with bump interconnects.
There are a number of conventional processes for packaging integrated circuits. Many packaging techniques use solder bumps onto associated I/O contact pads formed on an active face of a die to provide electrical interconnects to external devices. The die is then typically attached to a suitable substrate, such as a printed circuit board (“PCB”), such that the solder bumps on the die are surface mounted to contact pads on the substrate. The solder bumps are then typically reflowed to form solder joint connections between the substrate and the attached die. Such a surface mount device (“SMD”) is often referred to as “wafer level chip scale package,” such as micro-SMD, wherein the die must be “flipped” to place its active surface containing solder bumps into contact with the substrate to which the chip is to be attached.
Various problems can occur when connecting a solder bump to a contact pad, such as issues with wetting, adhesion, temperature cycling induced stresses, and the electrical isolation needs. Often these problems are addressed by providing additional items between the solder bump and the contact pad. Such items can include, for example, under bump metallization (“UBM”) stacks. For purposes of efficiency, these items are all typically formed onto dice at the wafer level prior to separation. Many such formation processes are generally known to those skilled in the art. Contact pads are usually formed first onto an active surface of a wafer. Next, one or more passivation and/or resilient layers having individual vias corresponding to individual contact pads are added. A UBM stack is then formed over each contact pad (within the vias), such that the bottom of each UBM stack contacts its associated contact pad or an electrical connector to the contact pad.
A common UBM structure is an electroless nickel-gold (Ni—Au) UBM. Solder bumping of ICs having aluminum bond pads requires removing the insulating aluminum oxide layer from the bond pad surface and making good electrical connection to the underlying metal. In the Ni—Au process, oxide removal and surface activation is commonly done through zinc displacement plating, using a zincate solution. The bump is then formed by selective electroless plating of nickel in a wet chemical maskless process. Typically, prior to zincation, the wafer is pre-cleaned and the wafer backside is covered by a protective layer of resist. Electroless Ni—Au plating also requires that all exposed material other than the contact pads be passivated or covered with resist. The zincation process removes the aluminum oxide and replaces it with a thin layer of zinc. After zincation, nickel is deposited from a hypophosphate-based nickel bath. The thickness of the deposited nickel depends on the plating time, with typical deposition rates of 20-25 micrometers per hour. Finally, a thin layer of immersion gold is plated over the nickel to protect the surface from oxidizing. FIG. 4A shows a cross-section drawing of a typical prior art electroless Ni—Au UBM structure (400). The central layer (410) is the final metal pad. The electroless nickel (420) deposits in the passivation (430) opening, and widens over the top of the passivation (430) as the nickel bump height increases. The thin gold plating is not shown in FIG. 4A. As can be seen in FIG. 4A, there is only one big opening or via in the passivation (430). A schematic top view of the via is shown in FIG. 4B.
Since the electroless NiAu UBM is a mask-less process, the manufacturing cost is lower. However, the ion exchange and temperature cycling that occur during the creation of the UBM structure typically result in intrinsic and extrinsic residual stresses, respectively, in the UBM structure. These stresses may result in pad delamination and/or silicon catering, due to the low compliance of silicon. Thus, although existing UBM structures work well in many situations, there are ongoing efforts to further improve the UBM structures used in various integrated circuit devices, such that problems like those described above are minimized or eliminated.